Comments on: Review of Bitwise System’s QuickUSB 2.0 Module http://www.electrosizzle.com/2008/05/review-of-bitwise-systems-quickusb-20-module/ Warm up to Electrical Engineering. Wed, 17 Mar 2010 12:57:02 +0000 http://wordpress.org/?v=2.9.2 hourly 1 By: TheSizzle http://www.electrosizzle.com/2008/05/review-of-bitwise-systems-quickusb-20-module/comment-page-1/#comment-91 TheSizzle Thu, 14 May 2009 20:00:39 +0000 http://www.electrosizzle.com/?p=5#comment-91 Shan, It's hard to say what could be causing that kind of behavior. I would first check the physical connection between the pins. Then, I would use what ever tool your FPGA manufacturer provides to look at the digital logic. Altera has the SignalTap II embedded logic analyzer while Xilinx has the ChipScope analyzer. Also, I'm assuming that you've configured those data pins as Input/Output pins with some sort of tri-state buffer whose direction is chosen by whether or not the the REN or WEN pins are active. Obviously, if the data pins on the FPGA are configured as outputs always, you'll be able to read and not write. Good luck! TheSizzle Shan,
It’s hard to say what could be causing that kind of behavior. I would first check the physical connection between the pins. Then, I would use what ever tool your FPGA manufacturer provides to look at the digital logic. Altera has the SignalTap II embedded logic analyzer while Xilinx has the ChipScope analyzer.

Also, I’m assuming that you’ve configured those data pins as Input/Output pins with some sort of tri-state buffer whose direction is chosen by whether or not the the REN or WEN pins are active. Obviously, if the data pins on the FPGA are configured as outputs always, you’ll be able to read and not write. Good luck!

TheSizzle

]]> By: Shan http://www.electrosizzle.com/2008/05/review-of-bitwise-systems-quickusb-20-module/comment-page-1/#comment-89 Shan Mon, 27 Apr 2009 23:54:20 +0000 http://www.electrosizzle.com/?p=5#comment-89 Hi Sizzle, I am having a bit of trouble implementing the writing part of the Simple I/O model of QuickUSB. It seems like either WEN(the writing enable signal) is either not turned on, or maybe my FIFO block is messed up that nothing is being written to them. Reading, on the other hand, seems fine. Would you mind share some opinion on this problem? Because it seems really hard to debug the writing part... (cannot really write them to a text file anymore :( ) Thanks in advance! Shan Hi Sizzle,

I am having a bit of trouble implementing the writing part of the Simple I/O model of QuickUSB. It seems like either WEN(the writing enable signal) is either not turned on, or maybe my FIFO block is messed up that nothing is being written to them. Reading, on the other hand, seems fine. Would you mind share some opinion on this problem? Because it seems really hard to debug the writing part… (cannot really write them to a text file anymore :( ) Thanks in advance!

Shan

]]> By: Shan http://www.electrosizzle.com/2008/05/review-of-bitwise-systems-quickusb-20-module/comment-page-1/#comment-88 Shan Thu, 23 Apr 2009 21:57:08 +0000 http://www.electrosizzle.com/?p=5#comment-88 Hi Sizzle, That sounds almost like my project speed (15MB/S tops). Thanks! Shan Hi Sizzle,

That sounds almost like my project speed (15MB/S tops). Thanks!

Shan

]]> By: TheSizzle http://www.electrosizzle.com/2008/05/review-of-bitwise-systems-quickusb-20-module/comment-page-1/#comment-87 TheSizzle Mon, 20 Apr 2009 20:55:21 +0000 http://www.electrosizzle.com/?p=5#comment-87 Hi Shan, I ended up going with the Simple I/O Model. Since I was only writing data to and from RAM blocks in the FPGA with a fixed address space, not FIFOs particularly, I found this to be the easiest to implement. In testing, I achieved read speeds (from FPGA RAM to the computer) of anywhere from 11 to 20 MB/s, but it's difficult to tell whether the bottleneck was the device or my computer. Good luck! TheSizzle Hi Shan,

I ended up going with the Simple I/O Model. Since I was only writing data to and from RAM blocks in the FPGA with a fixed address space, not FIFOs particularly, I found this to be the easiest to implement. In testing, I achieved read speeds (from FPGA RAM to the computer) of anywhere from 11 to 20 MB/s, but it’s difficult to tell whether the bottleneck was the device or my computer. Good luck!

TheSizzle

]]> By: Shan http://www.electrosizzle.com/2008/05/review-of-bitwise-systems-quickusb-20-module/comment-page-1/#comment-86 Shan Mon, 20 Apr 2009 20:46:53 +0000 http://www.electrosizzle.com/?p=5#comment-86 Hi E. Sizzle, Out of curiosity, did you implement your project with QuickUSB module in master FIFO mode or in slave FIFO mode? If you are did it with master mode, how is your data rate? I hope you don't mind me asking because I am also implementing a similar project. Thanks. Shan Hi E. Sizzle,

Out of curiosity, did you implement your project with QuickUSB module in master FIFO mode or in slave FIFO mode? If you are did it with master mode, how is your data rate? I hope you don’t mind me asking because I am also implementing a similar project. Thanks.

Shan

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